San Jose, California, United States
6 months ago

Job Overview

Pay
The base salary range is $160,000.00 USD – $200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Job description

Salary:
USD 160,000 - 200,000 per year
Location:
San Jose, California, United States
Work arrangement:
On-site

Role Summary

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Astera Labs Inc. is seeking an experienced and self-driven Hardware Lab Engineer to join our dynamic team in developing world class connectivity products for AI infrastructure.

This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight.

Responsibilities

  • Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs.
  • Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces
  • Install and configure servers, including FW, BIOS, OS, and network
  • RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization
  • Manage logistics and communications with external labs
  • Organize, track, and distribute lab equipment, hardware, and peripherals
  • Ad hoc PCBA rework and soldering of fine-pitch SMD components
  • Develop, document, and maintain lab procedures

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 5-12+ years of hands-on experience in lab environments supporting silicon validation or hardware development
  • Proficiency with high-speed test equipment (oscilloscopes, protocol analyzers, BERTs, multimeters)
  • Experience with high-speed interface testing (PCIe, CXL, DDR, Ethernet, or SerDes)
  • Strong programming skills in Python for test automation
  • Familiarity with Linux operating systems and command-line tools
  • Demonstrated experience coordinating with third-party testing laboratories and managing logistics, including sample shipping, chain of custody, and scheduling
  • Strong organizational skills for managing multiple RMA cases simultaneously and prioritizing based on severity/impact

Preferred Qualifications

  • Experience with post-silicon validation of ASICs, SoCs, or Retimer/PHY products
  • Knowledge of analog/mixed-signal circuit testing and debugging techniques
  • Experience with JTAG, I2C, SPI, and other embedded interfaces
  • Familiarity with PCB design, schematic reading, and signal integrity concepts
  • Knowledge of data center systems architecture (servers, AI platforms, networking equipment)
  • Understanding of ATE (Automated Test Equipment) systems and production test methodologies
  • Experience with defect screening methodologies including visual inspection, electrical testing, and acoustic imaging
  • Experience with complete RMA lifecycle management from intake through root cause analysis and corrective action
  • Knowledge of common semiconductor failure modes and failure analysis techniques including die attach inspection, delamination detection, void analysis, and crack identification
  • Experience with formal compliance testing and industry standards

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Role:
Hardware Lab Engineer

Company profile

Astera Labs

asteralabs.com

Astera Labs designs semiconductor-based connectivity solutions for rack-scale AI infrastructure, addressing data, memory and networking bottlenecks with PCIe, CXL, Ethernet, UALink and NVLink Fusion technologies. Its products include Leo Smart Memory Controllers, Taurus Smart Signal Conditioners, smart retimers and redrivers, and the Scorpio X-Series fabric switch, and it works with hyperscalers and the data center ecosystem. Astera Labs co-founders Jitendra Mohan, Sanjay Gajendra and Casey Morrison won the EY World Entrepreneur of the Year 2026 title.

Company Size
500 - 1,000 employees
Headquarters
Santa Clara, California, United States
Founded
2017
Funding Stage
Public

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